SRAM and periphery specialized device sensors

ABSTRACT

A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

RELATED APPLICATION

The present application claims priority to U.S. Provisional ApplicationNo. 62/337,290 filed on May 16, 2016, and incorporates that applicationin its entirety by reference.

FIELD

The present invention relates to on-chip device sensing, and moreparticularly to SRAM device sensors.

BACKGROUND

Most existing process sensors are targeted towards the chip standardcore devices and are ill suited for static random access memory (SRAM)device process corner sensing, because SRAM bitcells do not use standardcore devices. Furthermore, the few process sensors designed for sensingSRAMs require “hacking” of the SRAM array and are targeted towards theoverall corner of the SRAM and incapable of detecting device skew.

BRIEF DESCRIPTION OF THE FIGURES

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 is block diagram of one embodiment of a system implementation ofa sensing, processing and compensation scheme including a plurality ofperipheral device and memory sensing modules; sensed data processing andevaluation, and compensation circuitries.

FIG. 2 is a block diagram of one embodiment of the device sensor networkof peripheral (core) and SRAM devices.

FIG. 3 is a circuit diagram of one embodiment of the device sensornetwork of peripheral (core) and SRAM devices.

FIG. 4 is a circuit diagram of one embodiment of one stage of a “READ”ring oscillator.

FIG. 5 is a circuit diagram of one embodiment of one stage of a “WRITE”ring oscillator.

FIG. 6 is a flowchart of one embodiment of the sensing and compensationsystem incorporating testing N-devices and of P-devices of a memoryarray and its periphery, of processing the sensed data, and ofactivating compensation circuitry.

FIG. 7 is a flowchart of one embodiment of a “READ” RO for testing theN-devices of a core (memory periphery) region.

FIG. 8 is a flowchart of one embodiment of a “READ” RO for testing theN-devices of an SRAM memory array.

FIG. 9 is a flowchart of one embodiment of a “WRITE” RO for testing theP-devices of a core (memory periphery) region.

FIG. 10 is a flowchart of one embodiment of a “WRITE” RO for testing theP-devices of an SRAM memory array.

FIG. 11 is a flowchart of the simulation, sensing and processing of dataand of the generation of compensation control signals.

DETAILED DESCRIPTION

The sensor compensation system described is designed to accuratelycharacterize in an integrated fashion the process corners of the uniquetypes of P-Devices and N-Devices of a CMOS chip that includes one ormore SRAM memory arrays. In one embodiment, the integrated circuit alsoincludes non-SRAM analog and digital devices utilizing core P-Devicesand core N-Devices. The sensor compensation system described is used, inone embodiment, to select Read and Write assist strategies of SRAMs.

In one embodiment, the circuit includes two ring oscillators (ROs), a“READ” RO for evaluating N-devices and a “WRITE” RO for evaluatingP-devices, an SRAM array, and a control-logic block controlling which ROand which type of device is activated.

In one embodiment, the SRAM array utilized in the evaluation process isa standard SRAM array, and does not need to be subjected to anymodification or alteration in order to implement the sensor compensationsystem of the present application. The SRAM array reflects the standardcompilation and usage of an SRAM bit-cell compiled to form an SRAMarray. Alternatively, the SRAM array may have any configuration ormodification. However, no modification is needed to enable the sensorcompensation system, in one embodiment.

The following detailed description of embodiments of the invention makesreference to the accompanying drawings in which like references indicatesimilar elements, showing by way of illustration specific embodiments ofpracticing the invention. Description of these embodiments is insufficient detail to enable those skilled in the art to practice theinvention. One skilled in the art understands that other embodiments maybe utilized and that logical, mechanical, electrical, functional andother changes may be made without departing from the scope of thepresent invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims.

FIG. 1 is a block diagram of one embodiment of the system in which thesensor compensation system may be implemented. The system is used, inone embodiment, to accurately detect the process corner of each of the Pand N devices of the chip core and of its memory array. A process cornerof a P-device or an N-device represents the extremes of parametervariations within the devices. A design should continue to function atthe device corners. In one embodiment, this data can be used for designtiming, power adjustments, SRAM memory array compensation in the form of“read-assist” or “write-assist”, and/or power and timing management ofthe SRAM array periphery such as word-line drivers and sense amplifiers.

Block 105 are the core and memory device sensors, including the “READ”RO and the “WRITE” RO for SRAM arrays and for the core and peripherydevices. The core & memory device sensors also include the control logicarbitrating which particular RO is active at any one time and the ROoutput sensors.

The data processing & logic 110, or central processing unit, comparesthe sensed outputs of the ROs to previous data, which may be pre-storedsimulation or silicon based evaluation. The data processing & logic 101issues control output signals. The control output signals utilizepre-determined logic that interfaces with logic and/or memory blocks forthe desired compensation scheme. An example of a system that mayimplement data processing & logic 110 is the Synopsys SMS (smart memorysystem) engine, such as the Synopsys DesignWare® Self-Test and Repair(STAR) Memory System®.

Blocks 115, 120, 125, and 130 are representative blocks that can beswitched into the circuit by data processing & logic 110. The system mayinclude one or more of the blocks 115, 120, 125, and 130. Blocks 115 and120 can provide a desired “read-assist” (block 115) and “write-assist”(block 120) for the SRAM memory arrays that are optimal for the sensedprocess corner. Activating blocks 115 and 120 in one embodiment turns onor off the desired switches in the peripheral blocks supporting the SRAMarray. Power management mechanism 125 and timing management mechanism130 may include word-line drivers, sense amps, and internal timinggenerators to optimize power consumption (power management mechanism125) and/or adjust read/write timing windows (timing managementmechanism 130). In one embodiment for example, the power managementmechanism 125 can reduce power consumed by the peripheral circuits bysetting the strength of drivers based on the characterization of theperipheral device. In one embodiment for example, the power managementmechanism 125 can optimize WL drive by the peripheral circuits bysetting the strength of drivers based on the characterization of theperipheral device.

Blocks 135 and 140 represent a typical compensated embedded SRAM designcontrolled by the power, timing management, read and write assistcircuits which were in turn generated based on the processed data of thememory 135 and peripheral device 140 sensors for optimal performance.One or more of such corrective elements may be used in the system, basedon the characterization of the circuit.

FIG. 2 is a block diagram of one embodiment of the device sensor networkof peripheral (core) and SRAM devices. The top level control circuitry205 provides control signals to control circuits. These control circuitsinclude, in one embodiment, periphery N-device “read” oscillator controlcircuitry 210, SRAM N-device “read” oscillator control circuitry 215,both of which output to a common read oscillator 230. Thus, in oneembodiment, a single read oscillator 230 reads both the periphery andSRAM N-devices. The output of the common read oscillator 230 is the readoscillation signal, which is used to evaluate the N-devices.

The control circuits include, in one embodiment, periphery P-device“write” oscillator control circuitry 220, SRAM P-device “write”oscillator control circuitry 225, both of which output to a common writeoscillator 235. Thus, in one embodiment, a single write oscillator 235writes to both the periphery and SRAM P-devices. The output of thecommon write oscillator 235 is the write oscillation signal, which isused to evaluate the P-devices.

FIG. 3 is a circuit diagram of one embodiment of the sensor networkencompassing the “READ RO” 305, the “WRITE RO” 310 and the control logic360 that determines which RO is active at any one time and whether it issensing an SRAM array device or a periphery/core device and what type ofdevice.

Block 305 is the main circuit and functionality scheme of one embodimentof the “READ” RO. The oscillating stages of the “READ RO” areimplemented in this embodiment with peripheral devices. The bitline (BL)node 315 loads alternating stages of the “READ RO” and discharges(leaking) through the weak N device leaker (325) when a peripheralN-device is being sensed or through the N-devices of the SRAM cell (335)when the SRAM array N-device is being sensed.

The “READ RO” in one embodiment is composed of the alternatingcontrolled stages and simple inverters (330). The frequency of the “READRO” is output at FREQ_RD (370). The output, in one embodiment, is thendigitized and fed to a processing unit (not shown here).

For sensing peripheral N-devices, the gate of the N-device gating thepath of the “weak read leaker” (325) is activated (HI) by the controlsignals RDLK-EN, tied to the gate of the N-device. RDEN_IN (365),MODE_IN, WREN_IN, (360) are configured to enable the P-devices (385 and386) of the “READ-RO” with source tied to VDD (a strong pull up in thisembodiment). The other P-device tied to the drain of P-device 385 ispart of the oscillator circuit. Also, with this configuration of thecontrol signals, in one embodiment the WL (380) of the memory array isturned off (LO).

In one embodiment, a stacked inverter is formed in part by P-device 385and weak read leaker N-device 325 components. The stacked inverter has 2P-devices and 2 N-devices, in one embodiment. One of the P-devices andone of the N devices are to “gate” the inverter, turning gated N-deviceOFF when the Read RO is used in Memory mode. In periphery node, gatedN-device is turned ON to make the leaky path an inverter and part of theoscillator. However, the P device gated by 385 is a part of theoscillator whether it is the periphery or the SRAM reading mode. Thegating N-device is either the “leaker” to the pass gate-pull downcombination or to the SRAM.

With this configuration the frequency (speed) of the “READ-RO” isdirectly impacted by the strength of the “weak read leakers” (325)present in alternating stages of the oscillator. A strong peripheralN-device will translate to a higher leakage current increasing thefrequency (speed) of the “READ-RO”. Similarly, a weaker peripheralN-device will translate to a lower leakage current reducing thefrequency (speed) of the “READ-RO”.

In one embodiment, sensing the N-device of the SRAM array utilizes thesame configuration as the control logic described above, enabling the“READ-RO” and disabling the “WRITE-RO” with two major differences: thesignal RDLK-EN gating the weak leaker is turned off (LO) blocking thepath of the weak leaker, and the WL (380) of the memory array is enabled(HI). With this setting the leakage path of the BL (315) of alternatingstages is through the enabled SRAM pull-down and pass-gate N-devices(335).

A strong SRAM N-device will translate to a higher leakage currentincreasing the frequency (speed) of the “READ-RO”. Similarly, a weakerSRAM N-device will translate to a lower leakage current decreasing thefrequency (speed) of the “READ-RO”.

In one embodiment, a “zero” should be written to the memory array priorto the sensing of the SRAM N-devices. In one embodiment, this isachieved through appropriate self-timing implemented through the controllogic and the word-line timing.

The “WRITE-RO” (310) operates in a similar fashion to the “READ-RO”(305) described above, with the main difference being that the BLB(bit-line-bar) (350) connected to alternating stages of the “WRITE-RO”(310) is charged through the P-pull-up of the SRAM bitcell (390) forSRAM bitcell P-device detection or through the “weak write leaker” (320)when the peripheral P-Device is being sensed.

Block 310 is the main circuit and functionality scheme of the “WRITE”RO. The oscillating stages of the “WRITE RO” are implemented in thisembodiment with peripheral devices. The BLB node (350) loads alternatingstages of the “WRITE RO” and charges (leaking) through the weak P deviceleaker (320) when a peripheral P-device is being sensed or through theP-devices of the SRAM cell (390) when the SRAM array P-device is beingsensed.

The “WRITE RO” in one embodiment is composed of alternating controlledstages and simple op-amps (355) performing the role of a “referenced”inverter. The choice of an op-amp in this embodiment is to increase thesensitivity of the inversion to a small amount of BLB (350) chargingthrough the “Weak Write Leaker” (320) in the case of peripheral P-devicesensing or through the pull-up/pass gate combination (390) of the SRAM.The frequency of the “WRITE RO” is output at FREQ_WR (375). In oneembodiment, it is further digitized and fed to a processing unit (notshown here).

For sensing peripheral P-devices, the control signals RDLK-EN tied tothe gate of the N-device gating the path of the “weak read leaker” (325)is de-activated (LO). The signals RDEN_IN (365) MODE_IN, WREN_IN, (360)are configured to enable “WRITE” RO. The BL pull-up device (385), theBLB pull-up device (386) and the N-device (395) are all activated (HI).N-device (396) is tied to the BLB node and is part of the oscillatorcircuit. Signal WRLK_ENB is turned on (LO) to enable the P-device gatingthe “weak Write Leaker” (320). With this configuration of the controlsignals the WL (380) of the memory array is turned off (LO), in oneembodiment.

The frequency (speed) of the “WRITE-RO” is directly impacted by thestrength of the “weak write leakers” (320) present in alternating stagesof the oscillator. A strong peripheral P-device will translate to ahigher leakage current increasing the frequency (speed) of the“WRITE-RO” due to faster charging of BLB (345). Similarly, a weakerperipheral P-device will translate to a lower leakage current decreasingthe frequency (speed) of the “WRITE-RO”.

For sensing the P-device of the SRAM array the same configuration of thecontrol logic described above enabling the “WRITE-RO” and disabling the“READ-RO” is used, with two major differences. The signal WRLK-ENBgating the weak leaker is turned off (HI) blocking the path of the weakleaker, and the WL (380) of the memory array is enabled (HI). With thissetting the leakage path of the BLB (345) of alternating stages isthrough the enabled SRAM pull-up P-device (390) and pass-gate N-devices(350).

A strong SRAM P-device will translate to a higher leakage currentcharging BLB (345) increasing the frequency (speed) of the “WRITE-RO”.Similarly, a weaker SRAM P-device will translate to a lower leakagecurrent decreasing the frequency (speed) of the “WRITE-RO”.

One of skill in the art should understand that this is an exemplaryconfiguration of the circuit elements and control signals which make upthe sensor compensation system. Various elements may be substituted, asis known in the art, while the essential functionality remains the same.Circuits which were activated high, can be activated low, and viceversa, and various CMOS elements may be substituted with equivalentelements, while remaining within the scope of this disclosure.

FIG. 4 shows one embodiment of the “READ-RO” block, including the SRAMblock (430). The READ-RO block in one embodiment comprises a total oftwo inversions between the input IN_R (405) and the output OUT_R (410).The first stage is a “gated inverter” where the strong pull-up (440) andthe NE pull-down (445) are both turned ON while the word line (WL) (425)is turned off in the peripheral “READ-RO” mode.

In the SRAM “READ-RO” mode, the WL (425) is turned on, the strongpull-up (440) is also turned on, but the NE pull down (445) is turnedoff.

In both modes, in one embodiment, the BL of the memory array loads thefirst stage. The second stage 420 is a simple inverter. In oneembodiment, there is a gated pull-up PUR (450) to control thepre-charging of the BLB (bit line bar) (455) for cell content stability.

In both modes of “READ-RO” operation the propagation delay of the twostages comprising this block is determined by the rate of leakage of theBL (435) as described in the previous section.

FIG. 5 shows one embodiment of one stage of the “WRITE-RO” including anSRAM block. It is composed of two levels of inversions, in oneembodiment. The first stage is composed of the inverter with theN-device pull down NDR (530) with input IN_W (540) being the input ofthe stage, and the pull-up P-device PUR (570) turned off (signal EB1disabled). The BLB (520) is part of the output of the first inverter, sois the weak leak path composed of the always-on leaker pull-up PLK (555)gated by the pass P-device PE (525) which is enabled when the “WRITE-RO”is in periphery sense mode. The BLB (520) is also tied to thealternative “leak” path of N-device PR and N-device N-AXR (515) of theSRAM bitcell with N-AXR gated by the WL. This leak path is turned off(WL=0) when peripheral “WRITE-RO” is in periphery sense mode and isturned on (WL=HI) when the “WRITE-RO” is in SRAM sense mode.

In one embodiment, the second stage is op-amp (535) with the referencevoltage VREF as one of the inputs to the op-amp (535) while the otherinput is tied to BLB (520), the output of the first stage also sensitiveto the “leak path” whether it is through the weak leaker PLK (555) orthe pull-up/pass-gate combination (515) of the SRAM bit-cell.

SEB (550) is a power-up/power down control signal for the op-amp (535).In one embodiment, signal EB0 (575) is asserted (HI) to ensure that BL(580) is pulled down through N-device NDL (565) to ensure a “zero” iswritten into the cell when in write-mode operation.

FIG. 6 is a flow chart of one embodiment of using the sensorcompensation system. Blocks 605 and 610 stress the fact that theperipheral/core devices and the SRAM array devices are highlyun-correlated and therefore the detection of the process corner for thedevices of each type should be done in isolation of the other. Block 605includes isolating the impact of the memory array while evaluating theperipheral devices, and block 610 includes isolating the peripheraldevices while evaluating the memory array. This applies to both theP-device and N-device evaluation of core/periphery vs. memory array. Theperipheral device corner for the P-device is characterized by pre-chargeof a bitline-bar (BLB) through the peripheral P-device to detect theperipheral P-device corner through a pre-charge operation. Theperipheral N-device characterized by discharge of the bitline (BL) todetect the peripheral N-device corner through a leak operation.

Block 615 addresses the process of sensing the corner of the P-Device ofthe memory array. As noted above, this is done with the leakage path ofthe core P-device core/periphery isolated. It utilizes a write operationwhere the strength of the P device of the SRAM bitcell is the dominantfactor in determining the speed of the “WRITE-RO”. The systemcharacterizes the P-devices of the SRAM by charging the bitline-barthrough bit-cell P-devices of the SRAM array, through a write operation.

Block 620 addresses the process of sensing the corner of the N-Device ofthe memory array. This is done with the leakage path of the N-device ofthe core/periphery isolated. It utilizes a read operation where thestrength of the N devices of the SRAM bitcell is the dominant factor indetermining the speed of the “READ-RO”. Characterizing the N-devices ofthe SRAM is done by discharging the bitline through bit-cell N-devicesof the SRAM array through a read operation.

Block 625 determines the process corner of each device. In oneembodiment, it also determines the deviation from the ideal processcorner. In one embodiment, this may be done by an on-chip processorengine (such as Synopsys SMS) that has silicon based data or simulationbased data stored in it, that also processes the data sensed by the“READ-RO” and WRITE-RO” for each of the peripheral and SRAM P and Ndevices. In another embodiment, this may be done by a separate circuitor system.

In one embodiment, the processor may activate control systems tocompensate for the variability of the SRAM device, based on the results.In one embodiment, the processor generates various control signals basedon pre-determined schemes that control various power, timing, and memoryassist control schemes. These control signals are switched into thecircuit based on the result of the calculation, to compensate for SRAMand/or or peripheral device issues. This is an example of thefunctionality of the processor. It is by no means restricted to suchfunctionality.

Blocks 635 and 640 address two typical applications of the use of thesensed data in control and compensation schemes for SRAM arrays and forperipheral/IO circuitry.

Block 630 addresses the use of the sensed strength and process corner ofthe peripheral and SRAM array device to determine whether the circuitneeds to compensate, based on the variability detected for the SRAMarray and the periphery. In one embodiment, this may be done by theprocessor generating control signals that are used in control,adjustment, and compensation schemes for the SRAM arrays such as readand write assist circuits, and for the peripheral logic such asself-timing circuitry, WL drive, and sense amplifier circuits. If nocompensation is necessary, the process ends. Otherwise, in oneembodiment, it proceeds to block 635, 640, or both, based on the levelof compensation identified and the compensatory options available.

Block 635 addresses the use of control signals generated based on thesensed data of the SRAM arrays to determine (by switching circuitry onor off) the magnitude of the read assist and write assist applied. Thisenhances SRAM yield.

Block 640 addresses the use of control signals generated based on thesensed data of the peripheral devices to determine (byenabling/disabling circuitry) the drive strength of the WL driver, andthe timing of the SRAM block. If no compensation is needed, the processends at block 650.

FIG. 7 is a flowchart detailing one embodiment of the procedure forperiphery N-device evaluation using a “READ-RO”. Block 705 outlines thestep of disabling any leakage path through the SRAM ARRAY by switchingoff all word-lines (WL) addressing the memory. Block 710 outlines thestep of enabling all gated devices in the path constituting the“READ-RO” for peripheral sensing. Block 715 notes that the system turnson of the peripheral “weak leaker” devices as outlined above. The“leakage” of nodes connected to BL(s) in the “READ-RO” determines thespeed of the “READ-RO”. Finally, block 720 describes the process ofsensing the frequency of the “READ-RO” at the output of the “READ-RO” asa proxy for sensing the process corner of the peripheral N-device. Thisfrequency is used to evaluate the weak leaker, as was described above.

FIG. 8 is a flowchart detailing one embodiment of the SRAM arrayN-device evaluation using a “READ-RO”. Block 805 outlines the step ofenabling the leakage path through the SRAM ARRAY by switching on theword-lines (WL) addressing the memory. Block 810 addresses turning onall the required gated devices in the “READ-RO”. Block 815 specificallyaddressing turning off the “weak leaker” of the peripheral path. Finallyblock 820 describes the process of sensing the frequency of the“READ-RO” at the output of the “READ-RO” as a proxy for sensing theprocess corner of the SRAM array N-device.

FIG. 9 is a flowchart detailing one embodiment of the procedure forperiphery P-device evaluation using a “WRITE-RO”. Block 905 outlines thestep of disabling any leakage path through the SRAM ARRAY by switchingoff all word-lines (WL) addressing the memory. Block 910 outlines thestep of enabling all gated devices in the path constituting the“WRITE-RO” for peripheral sensing. Block 915 emphasizes the turning onof the peripheral “weak leaker” devices as discussed above. The“leakage” of nodes connected to BLB(s) in the “WRITE-RO” determines thespeed of the “WRITE-RO”. Finally block 920 describes the process ofsensing the frequency of the “WRITE-RO” at the output of the “WRITE-RO”as a proxy for sensing the process corner of the peripheral P-device.

FIG. 10 is a flowchart detailing one embodiment of the SRAM arrayP-device evaluation using a “WRITE-RO”. Block 1005 outlines the step ofenabling the leakage path through the SRAM ARRAY by switching on theword-lines (WL) addressing the memory. Block 1010 addresses turning onall the required gated devices in the “WRITE-RO”. Block 1015specifically addressing turning off the “weak leaker” of the peripheralpath. Finally block 1020 describes the process of sensing the frequencyof the “WRITE-RO” at the output of the “WRITE-RO” as a proxy for sensingthe process corner of the SRAM array P-device.

FIG. 11 is a flowchart of one embodiment of an overall system thatinvolves simulation of the sensor circuits to establish a reference,sensing silicon, processing the results and, utilizing the processeddata to generate compensation and control signals for further use with aCMOS silicon on insulator (SOI) design in general and an SRAM array andits periphery in particular.

Block 1105 reflects the step of using HSPICE (or another circuitsimulator, or data from an earlier characterized silicon) to simulatethe “READ-RO” and “WRITE-RO” under different global corners, dosensitivity analysis simulations. In one embodiment, this data is usedto set references for global corners and derating curves for variationaround global corners for both peripheral and SRAM array ROconfigurations, In one embodiment, this data is stored in the “A”registers of a processor, at block 1110.

Block 1115 reflects silicon characterization of the “READ-RO” and“WRITE-RO” for each of the peripheral and SRAM array devices. In oneembodiment, this characterization is the process described above withrespect to FIGS. 7-10. In one embodiment, the data is stored in “B” theregisters of a processor block 1120.

In block 1125 a processing engine (such as Synopsys SMS) is used tocompare the simulation data and the measured results, e.g. the data inthe “A” and B″ registers. The processing in one embodiment generatesvariation data analysis and uses designed planned schemes.

Block 1130 reflects the generation of control and compensation signalsgenerated by the processing engine based on the planned scheme. Thesecontrol signals are used to switch in compensation circuitry or adjusttiming, as described above, with respect to FIG. 6, in one embodiment.Although this process has been described in particular with respect toSRAM and periphery devices, one of skill in the art would understandthat such evaluations may be made in other types of devices, includingmemory peripheral systems and supporting logic.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

We claim:
 1. An apparatus comprising: a plurality of peripheralP-devices, the peripheral P-devices characterized by being pre-chargedby a bitline-bar (BLB) through the peripheral P-devices to detect aperipheral P-device process corner through the pre-charge operation; anSRAM array characterized by pre-charging the BLB through P-devices ofthe SRAM array to detect an SRAM array's P-device process corner througha write operation; and a write ring oscillator used to characterize theperipheral P-devices and the P-devices of the SRAM array.
 2. Theapparatus of claim 1, further comprising: a plurality of peripheralN-devices, the peripheral N-devices characterized by discharge of abitline (BL) to detect a peripheral N-device process corner through aleak operation; the SRAM array further characterized by discharging thebitline through bit-cell N-devices of the SRAM array through a readoperation; and a read ring oscillator used to characterize theperipheral N-device and the N-devices of the SRAM array.
 3. Theapparatus of claim 2, wherein the read operation is through a pluralitymemory cells along a bitline.
 4. The apparatus of claim 2, wherein aplurality of memory SRAM arrays each have an associated peripheralP-device and an associated peripheral N-device, to characterize theplurality of memory arrays.
 5. The apparatus of claim 4, wherein aglobal variation in the N-devices and the P-devices in an integratedcircuit is calculated based on the characterization of the plurality ofmemory arrays.
 6. The apparatus of claim 5, further comprisingcompensating for a local variability impact of SRAM device sensing,based on the plurality of memory arrays.
 7. The apparatus of claim 5,further comprising: a first memory storing simulation data for asimulated SRAM device to establish a reference; a second memory storingsensed data from characterization of the SRAM array; a processor toprocess the simulation data and the sensed data, and to generate controland compensation signals when the processing determines thatcompensation is needed to compensate for a variability of the SRAMdevice.
 8. The apparatus of claim 4, further comprising: correctiveelements used with the apparatus to compensate for a variability in thememory arrays of an integrated circuit.
 9. The apparatus of claim 1,further comprising one or more of: a read assist circuit, switched intothe SRAM array when the characterization indicates that compensation isneeded, and a write assist circuit, switched into the SRAM array whenthe characterization indicates that compensation is needed.
 10. Theapparatus of claim 1, further comprising: a power management mechanismto reduce power consumed by a peripheral circuit elements by setting astrength of drivers based on the characterization of the peripheraldevice.
 11. The apparatus of claim 1, further comprising: a powermanagement mechanism to optimize WL drive by the peripheral circuits bysetting a strength of drivers based on the characterization of theperipheral device.
 12. The apparatus of claim 1, further comprising: acontrol signals to optimize timing circuitry of the SRAM based on thecharacterization of the peripheral device.
 13. A method to characterizean integrated circuit comprising: characterizing a peripheral P-device,and P-devices in an SRAM array through a precharge and write operationusing a write ring oscillator to identify process corners for theperipheral P-device and the P-devices in the SRAM array; characterizinga peripheral N-device, and N-devices in the SRAM array through a readoperation using a read ring oscillator to identify process corners forthe peripheral N-device and the N-devices in the SRAM array; calculatinga global variation in the N and P devices in the integrated circuitbased on the characterization of a plurality of peripheral N-devices, aplurality of peripheral P-devices, and a plurality of SRAM arrays. 14.The method of claim 13, further comprising: generating control andcompensation signals when the calculating determines that compensationis needed for variability of the SRAM device.
 15. The method of claim13, wherein the read operation is through a plurality memory cells alonga bitline.
 16. The method of claim 13, further comprising: calculating aglobal variation in the N-devices and the P-devices based on thecharacterization of the plurality of memory arrays.
 17. The method ofclaim 13, further comprising: compensating for a local variabilityimpact of SRAM device sensing, based on the plurality of memory arrays.18. The method of claim 13, further comprising: retrieving simulationdata for a simulated SRAM device from memory, the simulation data usedto establish a reference; receiving sensed data from characterization ofthe SRAM array; and processing the simulation data and the sensed datato generate control and compensation signals when the processingdetermines that compensation is needed to compensate for a variabilityof the SRAM device.
 19. The method of claim 13, further comprising oneor more of: switching a read assist circuit into the SRAM array when thecharacterization indicates that compensation is needed, and a writeassist circuit, switched into the SRAM array when the characterizationindicates that compensation is needed.
 20. The method of claim 13,further comprising: setting a strength of drivers based on thecharacterization of the peripheral device to reduce power consumed by aperipheral circuit elements.
 21. The method of claim 13, furthercomprising: setting a strength of drivers based on the characterizationof the peripheral device to optimize WL drive by the peripheralcircuits.